Memory Map

The ESP32-P4 has a multi-tier memory architecture with distinct regions for the high-performance (HP) system, low-power (LP) system, and external storage. This page documents the memory available on the ESP32-P4-WIFI6-DEV-KIT.

Memory overview

Region	Size	Type	Access
HP System ROM	128 KB	Mask ROM	Read-only. Contains first-stage bootloader and ROM functions.
LP System ROM	16 KB	Mask ROM	Read-only. Contains LP core boot code.
HP L2 Memory	768 KB	SRAM	Read/write. Primary fast memory for HP system code and data.
LP SRAM	32 KB	SRAM	Read/write. Retained during deep sleep for LP core use.
System TCM	8 KB	SRAM	Read/write. Tightly-coupled memory for latency-critical operations.
PSRAM	32 MB	Octal SPI PSRAM	Read/write. Stacked in package. Higher latency than internal SRAM.
NOR Flash	16 MB	QSPI NOR Flash	Read/write (with erase). External chip. Stores firmware and data partitions.

Internal SRAM (HP L2 Memory)

The 768 KB HP L2 memory is the primary working memory for the dual-core HP system. It is accessed through the L2 cache and supports both instruction fetch and data access.

Key characteristics:

• Single-cycle access through the cache
• Partitioned between instruction and data by the MMU
• Available for DMA transfers
• Lost on power-off or deep sleep (not retained)

Note

The ESP32-P4 uses an L2 cache between the CPU cores and the L2 memory. Cache line size and associativity are configurable through the MMU. Refer to the ESP32-P4 Technical Reference Manual for cache configuration details.

Low-power SRAM

The 32 KB LP SRAM is accessible by the LP (low-power) RISC-V core. It is retained during deep sleep, making it suitable for:

• LP core program storage during sleep
• Persistent variables across sleep/wake cycles
• RTC-controlled wake-up logic data

Tightly-coupled memory (TCM)

The 8 KB system TCM provides deterministic, zero-wait-state access for latency-critical code and data. Unlike L2 memory, TCM access bypasses the cache, guaranteeing consistent access times regardless of cache state.

Typical uses:

• Interrupt handlers requiring deterministic timing
• Real-time control loops
• DMA descriptor tables

External PSRAM (32 MB)

The 32 MB octal SPI PSRAM is stacked inside the ESP32-P4 package (the “NRW32” variant). It is accessed via an octal SPI interface through the SPI cache controller.

Parameter	Value
Capacity	32 MB (256 Mbit)
Interface	Octal SPI
Max clock	Varies by operating mode
Access	Memory-mapped via cache
Retention	Lost on power-off

Tip

PSRAM is ideal for large buffers (frame buffers, audio buffers, network packet pools) that do not fit in the 768 KB internal SRAM. Access latency is higher than internal SRAM due to the SPI interface and cache misses. Place latency-critical data in internal SRAM or TCM.

PSRAM usage guidelines

• Frame buffers: A single 1080p RGB888 frame requires approximately 6 MB. PSRAM is the only practical location for display and camera frame buffers.
• Audio buffers: I2S DMA buffers for audio playback and capture.
• Heap allocation: ESP-IDF can extend the heap into PSRAM for malloc allocations. Use heap_caps_malloc(size, MALLOC_CAP_SPIRAM) for explicit PSRAM allocation.
• WiFi/Bluetooth buffers: The ESP32-C6 co-processor communication uses shared buffers that may reside in PSRAM.

External NOR Flash (16 MB)

The 16 MB QSPI NOR flash is an external chip on the board (component 3). It stores:

Region	Typical Use
Bootloader	Second-stage bootloader
Partition table	Defines flash layout
Application	Firmware binary (OTA-capable with two app slots)
NVS	Non-volatile storage for configuration key-value pairs
Filesystem	SPIFFS or LittleFS partition for file storage
Coredump	Crash dump storage (optional)

Caution

NOR flash has a limited write endurance (typically 100,000 erase cycles per sector). Avoid frequent writes to the same flash sector. Use NVS (which includes wear leveling) for configuration data rather than raw flash writes.

Flash partition layout

The partition table is user-configurable. A typical layout for this board:

# Name,     Type, SubType,  Offset,   Size
nvs,        data, nvs,      0x9000,   0x6000
phy_init,   data, phy,      0xf000,   0x1000
factory,    app,  factory,  0x10000,  0x200000
storage,    data, spiffs,   0x210000, 0xDF0000

The exact layout depends on your application requirements. ESP-IDF’s menuconfig or a custom partitions.csv file defines the partition table.

Memory map summary

Address Space (simplified)
-----------------------------------------
Internal:
  HP L2 Memory    768 KB   Fast SRAM
  LP SRAM          32 KB   Retained in deep sleep
  TCM               8 KB   Zero-wait-state
  HP ROM           128 KB   Boot + ROM functions
  LP ROM            16 KB   LP boot code

External (memory-mapped via cache):
  PSRAM             32 MB   Octal SPI, in-package
  Flash             16 MB   QSPI, external chip

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Memory specifications sourced from the ESP32-P4 Datasheet and Waveshare ESP32-P4-WIFI6-DEV-KIT Wiki.